1. Field of the Invention
The invention relates to the field of memory technologies, and in particular, to double-sensing of a memory cell being read to improve overall memory read access speed.
2. Description of Related Art
In a computer system including a high-speed microprocessor, the access speed of the cache memory is critical in determining the cycle time of the computer system, and can be a limiting factor preventing a microprocessor from realizing its full performance potential. One factor determining the access speed of a particular memory device is the scheme used to detect the contents of the memory. Differential sensing is one well-known approach. FIG. 1 illustrates an example of a differential sensing scheme used to read the contents of an MOS RAM array. As shown, each memory cell in the array, such as memory cell 1-1 provides its output on two complementary bit lines such as bit lines 10 and 11 for memory cell 1-1. Differential sensing operates by sensing a differential signal between the two complementary differential output bit lines coupled to a particular memory cell with a sensing device such as the sense amplifier 13. The differential signal is then decoded by the sense amplifier to determine the value stored in the memory cell.
High precision sense amplifiers are now available which can sense very small differences (100-200 mV) between the complementary output bit lines. However, unpredictable effects on the bit line pairs, such as voltage drop and alpha particle effects, may operate to reduce the differential sensing speed, and thus, increase the memory access speed, by increasing the time necessary to generate a detectable differential signal.
As mentioned, the above detrimental effects on the bit line pairs are unpredictable. Further, the access time push-out caused by these effects tends to be somewhat data pattern-sensitive. To guard against data integrity issues which might be caused by sensing the differential signal too early, existing memories are limited to an access time which takes into account the worst case combination of effects on the development of the differential signal. In other words, the sense amplifier is only enabled after a delay calculated to ensure, even in the presence of voltage drop, alpha particle and/or other effects, that the required minimum differential has developed between the bit line signals. The self-timing circuit 14 of FIG. 1, for example, imposes this delay regardless of whether a particular sensing operation is affected in this manner or not.
Thus, it is desirable to be able to speed up memory access by avoiding the delay imposed to account for detrimental effects on the sensed signal when a particular sensing operation is not affected. It is further desirable to be able to do so without compromising data integrity or robustness.